1. Field of the Invention
The present invention relates generally to integrated circuit device fabrication employing multiple semiconductor materials, and more specifically to integration of distinct semiconductor materials selected to optimize the speed of an integrated circuit including devices formed within each of the semiconductor materials.
2. Description of the Prior Art
Materials and device physics for commercial solid state semiconductor device fabrication have progressed through a wide spectrum of materials, material combinations, and device structures. Starting with the Germanium (Ge) point contact transistor in 1948, developments progressed in the 1950s through single-crystal Ge devices, Ge bipolar junction transistors (BJTs), Ge junction field effect transistors (JFETs), single crystal silicon (Si) devices, and silicon bipolar junction transistors. After development of silicon planar bipolar junction transistors and silicon metal oxide semiconductor field effect transistors (MOSFETs) in the early 1960s, together with Gallium Arsenide (GaAs) devices a few years later, progress on use of specific materials slowed until the latter half of the 1980s, with development of GaAs on Si devices and SiGe/Si heterojunction bipolar transistors (HBTs). In this decade, development of materials technology in semiconductor device fabrication has progressed from GaAs on Si and SiGe/Si through GaAs metal semiconductor field effect transistors (MESFETs), Si complementary metal oxide semiconductor (CMOS) devices, SiGe/Si metal oxide semiconductor (MOS) devices, Aluminum Gallium Arsenide-Germanium-Gallium Arsenide (AlGaAs/Ge/GaAs) HBTs, and GaAs MOS devices.
For at least a decade, silicon MOS and CMOS technologies have been the mainstay of commercial semiconductor device fabrication, with advances in device feature size into the submicron range providing improvements in device performance. As very large scale integration (VLSI) technology pushes toward smaller geometries, however, the transistor channel length and the parasitic resistive-capacitive (RC) constant finally limit circuit speed. The transistor switching (propagation) delay tpd of a CMOS device, which is a function of the device load capacitance, the drain voltage, and the saturation currents for both the n-channel and p-channel devices, limit the maximum operating frequency for an integrated circuit device.
Improvement of performance in contemporary silicon MOS and CMOS processes through reduction of feature sizes, which are already less than 0.18 xcexcm for CMOS channel lengths, is becoming increasingly difficult. Additionally, the electrical properties of silicon itself, particularly charge carrier mobility, are an increasingly significant limitation of device performance. For shorter device channel lengths, for example, carrier mobility (xcexc, typically expressed in units of cm2/Vxc3x97sec) becomes an increasingly contributor to propagation delay. Accordingly, different combinations of semiconductor materials having different, beneficial electrical characteristicsxe2x80x94such as SiGexe2x80x94are currently being explored.
It would be desirable, therefore, to improve circuit speed in semiconductor integrated circuits, particularly through use of commercially viable materials and processing technology. It would further be advantageous to employ distinct semiconductor materials to take advantage of the best electrical properties of different materials.
A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer, significantly lessening the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 xcexcm to avoid hot carrier degradation while still achieving performance increases over 0.18 xcexcm silicon-only CMOS integrated circuits.